Co-planar barrier-type charge coupled device with enhanced storage capacity and decreased leakage current

ABSTRACT

A charge coupled device is disclosed which includes a plurality of stages having increased charge storage capacity and decreased leakage current. Each stage is comprised of a semiconductor substrate of a first-type conductivity having a first surface. An insulating layer of uniform thickness lies on the first surface. A charge transfer channel extends through each stage. Phase electrodes lie on the insulating layer transversely to the channel. The semiconductor substrate under each phase electrode is divided into a barrier region and an adjacent well region bounded by the channel. A shallow dopant layer of the first-type conductivity lies in each of the barrier regions relatively near to the first surface. A buried channel dopant layer of a second-type conductivity lies in the well regions and the barrier regions under and relatively near to the shallow first-type conductivity dopant layer. Additionally, an enhanced first-type conductivity dopant layer lies in the well regions and the barrier regions under and relatively near to the buried channel dopant layer of second-type conductivity.

BACKGROUND OF THE INVENTION

This invention relates to semiconductor memories, and more particularlyto charge coupled device memories (CCD) comprised of improved memory"cells" or "stages".

During the past several years, much time, effort, and money has goneinto the development of high density, low cost memories. This is becausethe computer industry has continually demanded more and more storagecapacity. As a result of this past memory development work, the numberof stages per chip has increased from 16 to 64,000. In addition, thecost per stage has been decreased by a factor of approximately 200.

A popular architecture for the CCD memory is the serial-parallel-serial(SPS) organization. Information in the form of charge packets isserially loaded into a shift register. When the register is full, thecharge packets are loaded in parallel into a first in-first out stack.The charge packets are then moved in parallel through column transferchannels within the stack. At the stack output, they are loaded inparallel into another shift register. The charge packets are thenshifted serially into a detection device.

A major reason for the increase in the number of stages per chip hasbeen the development of small, reliable memory cells. Thousands of thesecells are formed on a single chip; and the chips are interconnected toform larger memories. By forming large numbers of memory cells in achip, large economies in the cost per bit can result if reasonableyields are obtained. However, as the size of a chip increases, the yielddecreases; so that the advantage of obtaining a large number of stagesper chip by use of a larger chip size is outweighed by reduction inyields. Presently, chips of about 150-250 mils on a side are commonlymade in the semiconductor industry. Accordingly, it is desirable toreduce the area occupied by each cell in order to further increase thenumber of stages per chip.

An important limitation of the prior art cells is that they all haveless charge capacity per unit area than is desirable. A high chargecapacity per unit area is desired because as the number of stages perchip increases, the size of each cell must necessarily decrease. Thusthe amount of charge stored in each cell decreases. Eventually, a pointis reached beyond which the cell cannot be reduced further because theamount of charge that the cell can store is indistinguishable fromnoise. Thus, charge capacity per unit area is a fundamental limitationon the minimum cell size.

Prior art cells are also deficient in a second parameter which is calledleakage current. The leakage current is a measure of the quantity ofelectron-hole pairs that are thermally generated in a cell. These chargecarriers are undesirable because they alter the amount of charge that isstored as information, and eventually they totally cancel theinformation charge. In order to avoid this cancelling effect, theinformation charge in the cell must be periodically "refreshed" atcertain minimum time intervals. The refresh period is inverselyproportional to the leakage current in the cell.

Because of these and other limitations in the prior art, and because ofthe demand for more cells of storage per chip, it is therefore an objectof this invention to provide an improved charge coupled device memory.

It is another object of the invention to provide a charge coupled devicememory comprised of stages having an increased storage capacity per unitarea.

It is still another object of the invention to provide a charge coupleddevice memory comprised of stages having decreased leakage current whileat the same time having increased storage capacity per unit area.

SUMMARY OF THE INVENTION

These and other objectives are accomplished in accordance with theinvention by a charge coupled device memory comprised of an array ofserial-parallel-serial memory blocks. The memory includes means forselectively addressing each of the blocks via address signals generatedexternal to the memory, and means for reading and writing data into eachof the selected blocks. The memory also includes control means forcontrolling the reading and writing operations in response to controland clocking signals generated external to the memory. Each of theblocks is comprised of an N-stage serial-parallel charge coupled deviceregister, an MXN-stage charge coupled device stack, and an N-stageparallel-serial charge coupled device register. The stack has N inputscoupled to N parallel outputs of the serial-parallel register. The stackalso has N outputs coupled to N parallel inputs of the parallel-serialregister. Thus, a serial-parallel-serial charge transfer channel isformed.

In one embodiment of the invention, each stage of the registers and thestack includes a P-type semiconductor substrate having a first surface.An insulating layer of uniform thickness lies on the first surface. Acharge transfer channel extends through each stage. At least two phaseelectrodes lie on the insulating layer transversely to the channel. Thesemiconductor substrate under each phase electrode is divided into abarrier region and an adjacent well region bounded by the channel. Ashallow P-type dopant layer lies in each of the barrier regionsrelatively near to the first surface. A buried channel N-type dopantlayer lies in the barrier regions and the well regions relatively nearto the shallow P-type dopant layer. An enhanced P-type dopant layer liesin each of the well regions and the barrier regions relatively far fromthe first surface having an acceptor doping which is greater than adoping of the P-type semiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are setforth in the appended claims; the invention itself, however, as well asother features and advantages thereof may best be understood byreferring to the following detailed description of particularembodiments when read in reference to the accompanying drawings,wherein:

FIG. 1 is a block diagram of a semiconductor memory constructedaccording to the invention;

FIG. 1a is a circuit diagram of a signal buffering circuit which may beincluded in the input/output logic forming part of the memoryillustrated in FIG. 1;

FIG. 2 is a block diagram illustrating in greater detail the structureof one of the memory blocks of FIG. 1;

FIG. 3 is a timing diagram illustrating the operation of the memoryblock of FIG. 2;

FIG. 4a is a cross sectional view illustrating the structure andoperation of a stage of the memory block of FIG. 2;

FIGS. 4b and 4c are potential diagrams illustrating the operation of thememory block stage shown in FIG. 4a;

FIG. 5 is a graph illustrating the relationship between gate tosubstrate voltage and channel potential in the stage of FIG. 4a;

FIG. 6 is a cross sectional view taken transversely to the chargetransfer channel of the stage of FIG. 4a; and

FIGS. 7a-7m are cross sectional views illustrating the process forconstructing the stage of FIG. 4a.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

Referring to FIG. 1, a block diagram of a charge coupled device memory(CCD memory) constructed according to the invention is illustrated. Thisparticular memory has a capacity of storing approximately 64,000 bits ofbinary information. The memory is implemented with charge coupleddevices (CCDs), and is fabricated on a single semiconductor chip.

Basically, the CCD memory consists of a storage array 10, address decodelogic 20, input/output logic 30, clock logic 40, and reference voltagelogic 45. Power is supplied to these components via loads 46. Storagearray 10 is basically comprised of sixteen serial-parallel-serial (SPS)memory blocks 11. Regeneration logic 12 is provided for each block. Eachof the sixteen blocks has a capacity of storing 4,096 bits of binaryinformation.

Address logic 20 selects one of the sixteen memory blocks 11 in responseto address signals A0-A3, CE and CS. The address logic may beimplemented with previously described logic means, an example of whichis described in IEEE Transactions on Electron Devices, Volume ED-23, pp.117-126, February 1976. The address signals are generated external tothe CCD memory, and are applied to the memory via leads 21. When signalCE is at a high voltage level and signal CS is at a low voltage level,address decode logic 20 is enabled. Decode logic 20 receives signalsA0-A3 on leads 21, decodes the A0-A3 signals, and generates selectionsignals on leads 22. Leads 22 selectively couple to one memoryblock-regeneration logic pair, and the signals generated thereon areinterpreted as selection signals.

Binary information is written into a selected SPS memory block in thefollowing manner. A lead 31 couples to input/output logic 30, and binaryinformation is applied to it from a source external to the CCD memory.Input/output logic 30 buffers the signal on lead 31 onto a lead 32. Lead32 couples to an input of the regeneration logic for each of the SPSmemory blocks, but signal on lead 32 is accepted only by the selectedblock. Any one of several regeneration structures may be used inconjunction with the memory blocks. An example of one such regenerationdevice is described in U.S. Pat. No. 3,979,603 issued to William M.Gosney on Sept. 7, 1976.

Similarly, binary information is read from a selected SPS memory blockvia leads 33 and 34. Lead 33 couples to an output of each of the SPSmemory blocks through the regeneration logic 12. A selected blockutilizes reference voltage signals formed by the reference voltage logic45 to sense the selected bits and generate information signals on lead33. Input/output logic 30 couples to lead 33 and buffers the signals onlead 33 onto lead 34. The buffered signals on lead 34 are sensed bylogic external to the CCD memory. An example of one circuit used tobuffer the signals on lead 33 is illustrated in FIG. 1a.

The above described write and read operation is further controlled bysignals R/W, CK1, and CK2. These signals are applied to the CDD memoryvia leads 35, 41, and 42 respectively. Lead 35 couples to input/outputlogic 30 and also drives a lead 36 which couples to the regenerationlogic 12 of each block. A high voltage on lead 35 is interpreted as aread command, and a low voltage is interpreted as a write command. Leads41 and 42 couple to each of the SPS memory blocks 11, and to clock logic40. Clock logic 40 receives signals CK1 and CK2 on leads 41 and 42, andin response generates clock signals SP1, SP2, P1, P2, P3, P4, PS1, andPS2. These signals control the timing of charge-transfers within SPSmemory blocks 11. Several leads 43 couple clock logic 40 to SPS memoryblocks 11 and carry the generated clock signals.

An important novel aspect of the above described CCD memory lies in thestructure of the cells within the SPS memory blocks 11. The novelstructure increases the charge capacity per unit area of each memorycell within block 11. This is a highly desirable result because for agiven cell surface area, the quantum of charge stored therein is easierto detect. Alternatively, a cell constructed according to the inventionmay be reduced in surface area and thereby increase the amount of memoryon a given chip size. The novel structure also results in a lowerleakage current. Thus, the time interval between refresh cycles may beincreased.

Referring then to FIG. 2, a block diagram (not to scale) of an SPSmemory block which incorporates the novel cells is illustrated.Basically, the memory block consists of an N-stage serial-parallelregister 50, an M×N stage stack 60, and an N-stage parallel-serialregister 70. Registers 50 and 70 have serial charge transfer paths 51and 71 respectively. Stack 60 has parallel charge transfer paths 61.Transfer paths 51, 61, and 71 are comprised of memory cells constructedaccording to the invention, and which will be described in detail inconjunction with FIGS. 4a-6.

Serial-parallel register 50 is comprised of a charge input device 53,and N serially connected stages 54. Charge input device 53 has an inputlead 55 for receiving data input signals. Device 53 generates chargepackets, representing a "0" or "1", in response to input signals on lead55. This charge is moved from stage to stage in a manner along chargetransfer path 51. Each stage includes first and second phase serialtransfer electrodes 56 and 57 to control the transfer of this charge.Leads 58 and 59 couple respectively to electrodes 56 and 57 of eachstage. Clock signals SP1 and SP2 are applied to leads 58 and 59respectively.

Stack 60 is comprised of a plurality of column channels 61 and columnchannel stops 62--the latter of which is illustrated as a double line.Each stage 54 of register 50 has an output region which couples to aninput 68 of one of the column channels. The channels and channel stopsalternate in parallel with each other, and are perpendicular to register50. Stack 60 includes a serial-parallel transfer electrode 63, aplurality of first and second phase parallel transfer electrodes 64 and65, and a parallel-serial transfer electrode 66 for moving chargethrough the column channels. These electrodes lie perpendicular to andextend across all of the channels. In addition, electrode 63 partiallyoverlies the output region of stages 54 in register 50. Leads 67 coupleto electrodes 63, 64, 65 and 66; and clock signals P1, P2, P3, P4respectively are applied to these electrodes to control the chargemovement.

Parallel-serial register 70 is comprised of N serially connected stages72 and one charge detection device 73. Each stage 72 has an input regionwhich couples to the output 69 of one column channel. Transfer electrode66 partially overlies the input region of register 70. Each stage 72includes first and second phase serial transfer electrodes 74 and 75 tocontrol the transfer of charge through the register. Leads 76 and 77couple respectively to electrodes 74 and 75; and clock signals PS1 andPS2 are applied thereto. Charge detection device 73 senses the presenceof absence of charge representing a binary "1" or binary "0" in the laststage, and generates an output signal on a lead 78 reflecting the sensedcharge level.

Referring to FIG. 3, a timing diagram of SPS memory block 11 isillustrated. This diagram explains one sequence in which charge is movedthrough the components of the memory block.

During a time interval 81, input device 53 injects charge packets inresponse to sequential digital input signals on lead 55. Clocks SP1 andSP2 alternate to move these injected charge packets through the N stagesof register 50. For an N-channel device, all the charge packets lie inpotential wells under electrode 56 when clock SP1 is at a high voltagelevel and clock SP2 is low. Conversely, when clock SP1 is low and clockSP2 is high, the charge packets move into potential wells underelectrodes 57. Thus, after N cycles of this SP1-SP2 clock sequence, eachstage of register 50 has a charge packet stored in it.

During a time interval 82, clock signal P1 is at a high voltage leveland the set of charge packets in register 50 moves in parallel from eachstage of register 50 in to stack 60 under electrode 63. Clock signalsSP1 and SP2 are both low during this time interval.

In a subsequent timing interval 83, clock signal P2 goes high and thecharge packets under electrode 63 move under an adjacent electrode 64.Also, the SP1-SP2 clock sequence continues and register 50 begins torefill.

During another time interval 84, clock P2 is low and clock P3 is high,and the charge packets in stack 60 move under electrodes 65. Also, theSP1-SP2 clock sequence continues to refill register 50.

In another time interval 85, clock P4 is high and charge packets moveunder electrode 66 from under the adjacent electrode 65. Note that thisis not the same set of charge packets that was moved from register 50into stack 60 during the preceding timer interval 82. Timing intervals83 and 84 must be repeated M times for one particular set of chargepackets to propagate through stack 60. Also during timing interval 85, anew set of charge packets may be moved from register 50 into stack 60.

In still another time interval 86, clocks PS1 and PS2 are sequenced tomove the charge packets into register 70 from under electrode 66, andthen serially through register 70 into detection device 73. Also, theSP1-SP2 clock sequence continued to refill register 50.

The detailed structure of each cell or stage of the memory block of FIG.2 will now be described in conjunction with FIG. 4a. FIG. 4a is a crosssectional view taken along the charge transfer paths 51, 61, or 71 ofFIG. 2. A typical cell along these paths is illustrated in FIG. 4a bythe structure enclosed within the dashed lines 90. As thereinillustrated, each stage includes a P-type semiconductor substrate 91having a first surface 92. An insulating layer 93 lies on top of surface92. Two phase electrodes 94 and 95 lie on insulating layer 93transversely to the charge transfer path through the stage. Phaseelectrodes 94 and 95 correspond to serial transfer electrodes 56 and 57in serial-parallel register 50. Similarly, phase electrodes 94 and 95correspond to parallel transfer electrodes 64 and 65 in stack 60. Also,phase electrodes 94 and 95 correspond to serial transfer electrodes 74and 75 in parallel-serial register 70.

The semiconductor substrate under each phase electrode 94 and 95 isdivided into a barrier region 96 and a well region 97. Region 96 liesadjacent to region 97. Both regions are bounded on their sides by chargetransfer channel stops such as channel stops 62 of FIG. 2 as example. AP-type dopant layer 98 lies in each of the barrier regions 96 relativelynear to first surface 92. In FIG. 4a, P-type dopant layer 98 isillustrated as a layer of minus signs representing an immobile positivecharge which remains in substrate 91 when the mobile charges of dopantlayer 98 have been depleted. In addition, a buried channel N-type dopantlayer 99 lies within regions 97 and 96 relatively near to shallow P-typedopant layer 98. Also according to the invention, an enhanced P-typedopant layer 100 lies within both the well region 97 and the barrierregion 96. The enhanced P-type dopant layer 100 lies within substrate 91at a distance relatively far from surface 92. The combination of dopantlayers 98 and 99, and enhanced P-type dopant layer 100 yields a buriedchannel charge coupled device having an increased depletion capacity andthus having an enhanced charge capacity. A detailed analysis of thisenhanced charge capacity will be described shortly in conjunction withFIG. 5.

The manner in which charge packets are transferred from one stage toanother is illustrated in FIGS. 4b and 4c. In particular, these figuresillustrate the surface potential φ_(s) along the surface of thestructure of FIG. 4a at two different time instants. In FIG. 4b, theclocking signals on phase electrodes 94 and 95 are on or at their activepotential, whereas in FIG. 4c the clocking signals on electrode 95 areoff. When a clocking signal is off, the surface potential on the barrierregion underlying the corresponding electrode is at a value φ_(s1), andthe surface potential in the well region underlying the correspondingelectrode is φ_(s2). Similarly, when a clocking signal is on, thesurface potential in the underlying barrier region is φ_(s3), and thesurface potential in the underlying well region is φ_(s4). For chargetransfer to occur from under one electrode to an adjacent electrode, thesurface potential φ_(s3) must be greater than the surface potentialφ_(s2). This condition is evident from inspection of FIG. 4c. Thecondition however can easily be met for a for a variety of clockvoltages, and charge distributions for dopant layers 98, 99, and 100.This fact along with a description of the increased charge capacity ofthe respective stages will now be described in conjunction with FIG. 5.

FIG. 5 illustrates surface potential in the well and barrier regions ofthe stage illustrated in FIG. 4a as a function of the gate to substratevoltage v_(gs). In particular, curve 110 relates surface potential tov_(gs) in the well region, while curve 111 relates surface potential tov_(gs) in the barrier region. Also contained in FIG. 5 are curves 112and 113 which relate surface potential to v_(gs) for a structure similarto that of FIG. 4a but which contains no N-type dopant layer 99 and noenhanced P-type dopant layer 100. Such a structure corresponds toconventional two phase CCD stages. As FIG. 5 illustrates, the effect ofadding an enhanced P-type dopant layer 100 in the barrier region 96 isto lower the surface potential in that region for any given gate tosource voltage. The reduction in surface potential however is anon-linear function of v_(gs). Note for example how curve 111 bends inthe region where v_(gs) varies. between 0 and 5 volts. The enhancedP-type dopant layer 100 has a similar effect on surface potential inregions 96 and 97. As a result, curve 110 has a slope for any givensurface potential which is greater than the slope of curve 111. Curve110 lies to the left of curve 111 due to the effect of N-type dopantlayer 99. That is, in the regions 96 and 97, the enhanced P-type dopantlayer 100 lowers the surface potential as a function of v_(gs) in anon-linear fashion, whereas N-type dopant layer 99 shifts the flatbandvoltage in a negative direction. FIG. 5 illustrates the surfacepotentials in a preferred embodiment wherein the density and depth ofthe enhanced P-type dopant layer 100 and N-type dopant layer 99 are suchas to shift the flatband voltage of regions 96 and 97 in a negativedirection by an amount in which the surface potential of regions 96 and97 at the active phase voltage is substantially the same as if the stagehad no enhanced P-type layer.

An analysis of the enhanced charge capacity of cell 90 will now bedescribed. In general, charge capacity of a cell is a measure of thequantum of charge which can be stored in a well region 97. It has beenshown that charge capacity equals a capacitance C times the gate tosubstrate voltage required to shift the surface potential of the wellregion to the surface potential of the barrier region. Referring to FIG.5, this change in v_(gs) is illustrated as Δv_(g) for a cell not havingan enhanced P-type dopant layer 100 and is illustrated as Δv_(ge) for acell having an enhanced P-type dopant layer 100. This is because theenhanced P-type dopant layer 100 caused curves 110 and 111 to have anon-linear curvature as previously described and thus a gate tosubstrate voltage difference between the two curves for a given φ_(s) isincreased.

In general, the curvature of curves 110 and 111 is increased as thedensity of P-type dopant layer 100 is increased. However, a limitationexists as to the extent to which the P-type dopant layer 100 chargedensity may be increased. This limitation is that the surface potentialφs₃ must be greater than φ_(s2). As the charge density of P-type dopantlayer 100 increases, φ_(s3) tends towards φ_(s2). Theoretically, chargestored in a potential well under one electrode is greater than or equalto the surface potential in the well under the first electrode. However,a voltage margin v_(m) is desired since it increases charge transferefficiency and makes the device more easily reproducible.

A cell having increased charge storage capacity and having a voltagemargin v_(m) may be constructed according to FIG. 4a wherein the densityand depths of the enhanced P-type dopant layer 100, N-type dopant layer99, and P-type dopant layer 98 have a wide range of values. For example,P-type dopant layer 98 may have a Gaussian distribution with a peaklying within 500 A-2000 A from surface 92, N-type dopant layer 99 mayhave a Gaussian distribution with a peak lying within 3000 A-10,000 Afrom said surface, enhanced P-type dopant layer 100 may have a Gaussiandistribution with a peak lying within 5000 A-15,000 A from surface 92.In this embodiment, the peak density of P-type dopant layer 98 isapproximately (1.0-50)×10¹⁷ ions/cm³, the peak density of N-type dopantlayer 99 is approximately (0.5-50)×10¹⁶ ions/cm³, and the peak densityof enhanced P-type dopant layer 100 is approximately (1.0-50)×10¹⁷ions/cm³. In an alternative embodiment, the enhanced P-type dopant layer100 may have a relatively uniform distribution extending from surface 92to approximately 5000-15,000 A below surface 92; and buried channellayer 99 may have a relatively uniform distribution extending from ontop of layer 100 to surface 92.

FIG. 6 is a cross sectional view of cell 90 taken across the chargetransfer path. Also indicated in FIG. 6 are the sources of leakagecharge generation. One of the sources is the depletion region underphase electrodes. This region is indicated in FIG. 6 by the dashed lines120. The amount of leakage current generated in depletion region 120 isproportional to the volume of the depletion region. The enhanced dopingwithin region 120 due to P-type dopant layer 100 results in a decreaseddepletion volume which in turn results in reduced leakage charge.

A second source of leakage charge is a component that is generated underthe thick field oxide region which borders the charge coupled devicechannel. These regions are indicated in FIG. 6 by the dashed lines 121.A finite depletion region exists within region 121. Further, thetransition from the field oxide region to the gate oxide region isgradual, extending over approximately 5000 A and this tapering producesa lateral grading in the surface potential resulting in an electricfield which aids in the transport of the charge carriers in the fieldregion to the storage well. By comparison, the structure disclosedherein has an enhanced P-type dopant layer 100 which extends into thetapered regions 121. Such a structure is achieved for example byimplanting the P-type layer at a relatively high energy such that someof the P-type ions penetrate directly into the tapered regions 121. Inaddition, the high energy implant causes the P-type ions to stragglelaterally into the transition region 121. As a result, an enhanceddoping layer is formed in the tapered region 121 which counteracts thesurface potential grading in those regions due to the tapered oxide. Infact, the density and implant energy of P-type dopant layer 100 can bechosen to actually reverse the field gradient within the tapered region121. As an example, a 250 KeV boron implant produces such a fieldgradient reversal. The enhanced capacity CCD stage 90 has a leakagecurrent 2 to 8 times less than conventional charge coupled devices dueto the mechanism.

Referring now to FIGS. 7a-7e, the initial steps for building a stageaccording to the invention are illustrated. These figures are crosssectional view taken transversely to the charge transfer path as wasillustrated in FIG. 6. The purpose of these initial steps is to form theperimeter of the stages (i.e., to define the charge transfer path). As afirst step, a silicon dioxide layer 140 is formed on surface 92 ofsubstrate 91. Layer 140 is approximately 1000 A thick. It is formed byexposing the silicon substrate to an oxidizing atmosphere atapproximately 1000° C. Next a silicon nitride layer 141 is formed on topof layer 140. Layer 141 is approximately 1000 A thick; and it is formedby exposing the substrate 91 to an atmosphere containing silane andammonia. Then a layer 142 of photoresist is deposited on top of thesilicon nitride layer 141. The photoresist may be of a type called KodakMetal Etch resist as an example.

The next several steps form field oxide regions and correspondingchannel stops along side stages. To this end, photoresist layer 142 isexposed to ultraviolet light through a mask having a pattern of thedesired charge transfer path channel stop pattern. The photoresist isthen developed leaving photoresist regions 143 as illustrated in FIG.7b.

The slice is next subjected to a selective etchant (wet chemical,plasma, or ion mill) which will remove the silicon nitride in the areaswhere the photoresist has been removed. Thus, only areas 144 of thesilicon nitride remain after this etching step. The result isillustrated in FIG. 7c. Next, a P-type implant is made through theexposed oxide layer to form channel stop regions 145a and 145b. Thesecorrespond to channel stops 62 of FIG. 2 for example. This implant stepmay be performed with boron ions at approximately 100 Kev. The dosage ofthese atoms is typically (0.1-1.0)×10¹³ ions/cm².

Next, photoresist regions 143 are removed by an appropriate clean-upstep and then field oxide regions 146a and 146b are grown. The latter isperformed by exposing the slice to an oxidation operation. The oxidationoperation involves exposing the slice to steam at approximately900°-1000° C. for several hours. During this operation, the nitrideareas 144 mask the oxidation where it exists. The oxide that is formedduring this process is approximately 3000 A-10,000 A thick. This oxidepenetrates the surface of the silicon to a depth of approximately 1500A-2500 A. However, the P+ regions 145a and 145b are only partiallyconsumed, and the remainder diffuse ahead of the oxidation front. Theresult of this operation is illustrated in FIG. 7d.

Then the nitride areas 144 are removed by an etchant, such as phosphoricacid. Next, oxide layer 140 is removed by another etchant, such ashydrogen fluoride. This completes the formation of the perimeter of thestage. The result is illustrated in FIG. 7e.

With reference to FIGS. 7f-7m, the remaining steps for constructingstages of a charge coupled device memory according to the invention willnow be described. FIGS. 7f-7m are cross sectional views taken parallelto one of the charge transfer paths 51, 61, or 71 of the memory block ofFIG. 2. First, as shown in FIG. 7f, gate oxide layer 93 is formed onsurface 92. The oxide layer 93 may be of any suitable thickness, andtypically is 500 A-1000 A. Thermal oxidation may be used to form layer93.

Next, enhanced P-type dopant layer 100 is implanted through oxide layer93 into substrate 91 throughout the channel regions. This step isillustrated in FIG. 7g. The charge density of layer 100 has a Gaussiandistribution, with the distribution peak lying approximately 5000A-15,000 A from surface 92. The peak charge density of layer 100 isapproximately (1.0-50) 10¹⁷ ions/cm³. In order that leakage current bereduced, the ions and implant energy are preferably chosen to lie withinthe perimeter of the channel stop regions, such as regions 121 of FIG.6. As an example, boron ions at an implant energy of 250 Kev may beutilized to achieve this straggle effect. Next, in order to provide theburied channel 131, an N-type dopant is implanted into substrate 91throughout the channel regions. The charge density of buried channel 131has a Gaussian distribution, with a distribution peak lyingapproximately 3000 A-10,000 A from surface 92. Note, that as analternative, the steps of FIGS. 7f and 7g may be reversed in sequence.That is, enhanced P-type dopant layer 100 and/or buried channel 131 maybe implanted directly into substrate 91 before gate oxide layer 93 isformed.

Using conventional photolithographic techniques, selected areas of thesilicon oxide layer 93 are masked and spaced apart strips 150 ofphotoresist material are defined along the length of the channel. P-typedopant ions, such as gallium, indium, or aluminum, are then implantedinto regions 151 of the silicon oxide layer between the photoresiststrips 150. Suitably, a beam energy of 55 KeV and dosage of(1.0-50)×10¹⁷ ions/cm² may be used. It is important that the beam energyis sufficient to implant the ions into the silicon oxide layer 93 butnot into the underlying surface areas of the substrate 91. Preferablythe dopant ions selected for the implant are characterized by a smallspread in penetration depth for the beam energy used so that a denselayer of dopant ions is formed in each of the implanted silicon oxideareas; and the impurity ions have a relatively large diffusioncoefficient in silicon oxide and a relatively low diffusion coefficientin silicon. The structure at this stage of the fabrication process isdepicted in FIG. 7h.

A layer of polycrystalline silicon is then deposited over the siliconoxide layer 93 and patterned by wet etching or plasma etching in offsetaligned relation to the implanted oxide areas 151 as illustrated in FIG.7i to define polycrystalline silicon strip electrodes 94 extendingacross the CCD channel in offset alignment relative to the implantedareas 151. A portion, (e.g., one-half) the length of eachpolycrystalline electrode 151 in the direction of the channel lengthoverlies part of each implanted area 151. The polycrystalline silicon isdeposited suitably at a temperature which is not high enough to resultin any appreciable out-diffusion of impurities from the areas 151 intothe underlying silicon substrate. A deposition temperature of 300°-800°C. may be used. The polycrystalline silicon layer may be doped duringdeposition to have a suitably high conductivity for providing of a goodelectrical conductor. Alternatively, it may be deposited undoped, andthen doped by ion implantation. An N-type impurity such as phosphoruscan be used with a beam energy of 90 KeV and a dose of 10¹⁵ -10¹⁶ions/cm² into 4000 A of polycrystalline silicon. This approach dopes thepolycrystalline silicon while avoiding use of high temperatureprocessing. In order to assist accurate alignment of the polycrystallinesilicon electrodes 94, alignment markers in the silicon oxide layer 93may be used.

With reference to FIG. 7j, the silicon oxide areas between theelectrodes 94 are then etched preferably using a wet etching process, toexpose the underlying surface areas of the substrate 91. In this manner,self-alignment of the shallow P-type implants 98 with respect to theedges of the polycrystalline electrodes 94 is achieved. This is animportant feature in order to achieve good CCD charge transferefficiency. If self-alignment were not achieved, stray potential wellsand barriers could result which would degrade the CCD transferefficiency.

Fresh silicon oxide is then formed, preferably using a thermal growthprocess, over the substrate surface areas between the electrodes 94.This results in silicon oxide areas having the same thickness as thesilicon oxide layers beneath the polycrystalline silicon electrodes 94and thus layer 93 is reformed. This oxide formation step also results ina layer 152 of silicon oxide covering the surface areas of thepolycrystalline silicon electrodes 94. The temperature used to form thissilicon oxide layer can be selected such that diffusion of the P-typedopant ions occurs out of the oxide areas 151 into the underlyingsurface areas 98 of the substrate. Alternatively, an additional hightemperature process step may be employed to achieve this diffusion. Thedopant impurities perferably are selected to have a relatively highdiffusion coefficient in silicon oxide and relatively low diffusioncoefficient in silicon.

A layer of photoresist is then formed over the structure shown in FIG.7l and patterned to define photoresist areas 153. Each photoresist area153 covers part (e.g., one-half) of the channel lying between electrodes94 and part of electrode 94. The uncovered areas of the silicon oxideregions define the barrier regions which will lie under electrodes 95 inthe completed structure. P-type dopant ions are then implanted into theunmasked portions of the silicon oxide regions. For example, galliumions and an implant energy of about 150 KeV and a dosage of 1.3×10¹²ions/cm² may be used. The structure is then subjected to a heattreatment, suitably in the range 800°-1000° C., to electrically diffusethe ions into substrate 91 thus forming shallow P-type implant 98.Alternatively, layer 98 under electrodes 95 may be implanted directlyinto substrate 91 through oxide layer 93.

Photoresist area 153 are then removed and a conductive layer, which maybe a metal layer, e.g., aluminum, or a conductive semiconductor layer,e.g., polycrystalline silicon, is then formed over the structure andpatterned to define electrodes 95 extending across the width of thechannel between the polycrystalline silicon electrodes 94. Electrodes 95have margins which overlap the edges of adjacent ones of the electrodes94 as shown in FIG. 7m. Typically, gate lengths of 0.2-0.5 mils mayreadily be achieved using this process.

The process described with reference to FIGS. 7a-7m can also be modifiedto construct a buried channel CCD by utilizing epitaxial growthtechniques. In order to construct a device using epitaxial growthtechniques, an enhanced P-type dopant layer is grown on the surface ofsubstrate 91 having a relatively uniform distribution and beingapproximately 5000 A-15,000 A thick. This enhanced P-type dopant layeris grown throughout the channel regions only. Typically, the epitaxialgrowth occurs at a temperature of 1000°-1200° C. in a gas of silicontetrachloride or silane. Dopants are introduced through a carrier gasand the dopant density is controlled by the partial pressure of thecarrier gas. A boron dopant for example may be introduced through acarrier gas of B₂ H₆. A uniform density of approximately (1.0-50)×10¹⁷ions/cm³ may suitably be obtained utilizing this process. Next, a buriedchannel layer is formed in the channel regions on top of the epitaxiallygrown enhanced P-type dopant layer. This buried channel dopant layer hasa relatively uniform distribution of approximately (0.5-50)×10¹⁶ions/cm³, and is approximately 3000-10,000 A thick. A phosphorus dopantfor example may be introduced through the carrier gas of PH₃. Next, thechannel stops are formed as described in conjunction with FIGS. 7a-7e;and then electrodes 94 and 95 are formed as previously described inconjunction with FIGS. 7h-7m.

It should be noted, that an alternative approach to increasing chargecoupled device storage capacity and decreasing leakage current in viewof what has been described above, may seen to simply choose substratematerial with a higher doping. However, one reason why it is undesirableto have a higher substrate doping throughout the entire substrate isthat the threshold voltage of peripheral circuitry on the chip willbecome too high. Another reason is that the body effect (thresholdvoltage dependence on back gate bias) is too large. Still another reasonis that junction capacitances and channel stop capacitances areincreased and limit the speed of the peripheral circuitry. Accordingly,an enhanced P-type dopant layer which lies throughout the chargetransfer channel but does not increase the substrate doping external tothe channel is a much more attractive approach to increasing chargecapacity and decreasing leakage current in a CCD structure.

Various embodiments of the invention have now been described in detail.Also, many changes and modifications can be made in the above describeddetails without departing from the nature and spirit of the invention.For example, P-channel devices as well as the above N-channel devicesmay be constructed. In order to construct a P-channel device, N-typematerial is substituted for P-type material, and vice versa. Chargedistributions and charge densities remain essentially as describedabove.

As another modification, the number of phase electrodes per stage may beincreased. For example, each stage may include three or four phaseelectrodes. As still another modification of the above details, thecharge coupled device memory may have an architecture which includes acharge transfer path other than a serial-parallel-serial charge transferpath. In fact, a straight serial charge transfer path may be utilized.In that case, the structure would be a charge coupled device registerhaving enhanced charge storage capacity and reduced leakage current.Since many changes and modifications can be made in the above-describeddetails without departing from the nature and spirit of the invention,it is understood that the invention is not limited to said detailsexcept as set forth in the appended claims.

What is claimed is:
 1. A charge coupled device comprising:a substrate ofsemiconductor material having a dopant impurity of P-type conductivity,said substrate having a first surface; a body of insulating materialdisposed on said first surface of said substrate; means defining aburied channel layer having a dopant impurity of N-type conductivity insaid substrate lying adjacent to said first surface of said substrateand providing a charge transfer channel; first and second spaced apartphase electrodes overlying said channel in transverse relation theretoand arranged with respect to said body of insulating material so as toprovide a layer of insulating material of uniform thickness between eachof said phase electrodes and said first surface of said substrate;spaced relatively shallow regions having a dopant impurity of P-typeconductivity lying within said buried channel layer of N-typeconductivity near said first surface of said substrate, each of saidrelatively shallow P-type conductivity regions extending beneath acorresponding one of said first and second phase electrodes and beingrespectively aligned adjacent one edge thereof but terminating short ofthe opposite edge of the electrode corresponding thereto; said substrateunder each of said first and second phase electrodes being divided intoa barrier region including a respective shallow P-type conductivityregion therein and an adjacent well region, said buried channel layer ofN-type conductivity extending through said barrier regions and said wellregions; an enhanced relatively deep layer having a dopant impurity ofP-type conductivity and of greater concentration than the P-typeconductivity dopant impurity in the semiconductor material of saidsubstrate disposed within said substrate at a depth spaced from saidfirst surface and extending through said barrier regions and said wellregions beneath said first and second phase electrodes; andthe P-typeconductivity dopant impurity of each of said relatively shallow P-typeconductivity regions having a Gaussian distribution with a peak lyingwithin 500 A-2000 A from said first surface of said substrate, theN-type conductivity dopant impurity of said N-type conductivity buriedchannel layer having a Gaussian distribution with a peak lying within3000 A-10,000 A from said first surface, and the P-type conductivitydopant impurity of said enhanced relatively deep P-type conductivitylayer having a Gaussian distribution with a peak lying within 5000A-15,000 A from said first surface.
 2. A charge coupled device as setforth in claim 1, wherein the P-type conductivity dopant impurity ofeach of said relatively shallow P-type conductivity regions has a peakdensity of approximately (1.0-50)×10¹⁷ ions/cm³, the N-type conductivitydopant impurity of said N-type conductivity buried channel layer has apeak density of approximately (0.5-50)×10¹⁶ ions/cm³, and the P-typeconductivity dopant impurity of said enhanced relatively deep P-typeconductivity layer has a peak density of approximately (1.0-50)×10¹⁷ions/cm³.
 3. A charge coupled device comprising:a substrate ofsemiconductor material having a dopant impurity of P-type conductivity,said substrate having a first surface; a body of insulating materialdisposed on said first surface of said substrate; means defining aburied channel layer having a dopant impurity of N-type conductivity insaid substrate lying adjacent to said first surface of said substrateand providing a charge transfer channel; first and second spaced apartphase electrodes overlying said channel in transverse relation theretoand arranged with respect to said body of insulating material so as toprovide a layer of insulating material of uniform thickness between eachof said phase electrodes and said first surface of said substrate;spaced relatively shallow regions having a dopant impurity of P-typeconductivity lying within said buried channel layer of N-typeconductivity near said first surface of said substrate, each of saidrelatively shallow P-type conductivity regions extending beneath acorresponding one of said first and second phase electrodes and beingrespectively aligned adjacent one edge thereof but terminating short ofthe opposite edge of the electrode corresponding thereto; said substrateunder each of said first and second phase electrodes being divided intoa barrier region including a respective shallow P-type conductivityregion therein and an adjacent well region, said buried channel layer ofN-type conductivity extending through said barrier regions and said wellregions; an enhanced relatively deep layer having a dopant impurity ofP-type conductivity and of greater concentration than the P-typeconductivity dopant impurity in the semiconductor material of saidsubstrate disposed within said substrate at a depth spaced from saidfirst surface and extending through said barrier regions and said wellregions beneath said first and second phase electrodes; and the N-typeconductivity dopant impurity of said N-type conductivity buried channellayer having a relatively uniform distribution extending from said firstsurface of said substrate to approximately 3000 A-10,000 A below saidfirst surface, and the P-type conductivity dopant impurity of saidenhanced relatively deep P-type conductivity layer having a relativelyuniform distribution extending from said N-type conductivity buriedchannel layer to approximately 5000 A-15,000 A below said first surface.4. A charge coupled device as set forth in claim 3, wherein the densityof the relatively uniformly distributed N-type conductivity dopantimpurity of said N-type buried channel layer is approximately(0.5-50)×10¹⁶ ions/cm³, and the density of the relatively uniformlydistributed P-type conductivity dopant impurity of said enhancedrelatively deep P-type conductivity layer is approximately (1.0-50)×10¹⁷ions/cm³.